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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. january 1995 copyright ? intel corporation, 1995 order number: 271328-001 special environment 80960CF-30, -25, -16 32-bit high-performance superscalar processor # socket and object code compatible with 80960ca # two instructions/clock sustained execution # four 59 mbytes/s dma channels with data chaining # demultiplexed 32-bit burst bus with pipelining y 32-bit parallel architecture e two instructions/clock execution e load/store architecture e sixteen 32-bit global registers e sixteen 32-bit local registers e manipulate 64-bit bit fields e 11 addressing modes e full parallel fault model e supervisor protection model y fast procedure call/return model e full procedure call in 4 clocks y on-chip register cache e caches registers on call/ret e minimum of 6 frames provided e up to 15 programmable frames y on-chip instruction cache e 4 kbyte two-way set associative e 128-bit path to instruction sequencer e cache-lock modes e cache-off mode y on-chip data cache e 1 kbyte direct-mapped, write through e 128 bits per clock access on cache hit y product grades available e se3: b 40 cto a 110 c y high bandwidth on-chip data ram e 1 kbytes on-chip ram for data e sustain 128 bits per clock access y four on-chip dma channels e 59 mbytes/s fly-by transfers e 32 mbytes/s two-cycle transfers e data chaining e data packing/unpacking e programmable priority method y 32-bit demultiplexed burst bus e 128-bit internal data paths to and from registers e burst bus for dram interfacing e address pipelining option e fully programmable wait states e supports 8, 16 or 32-bit bus widths e supports unaligned accesses e supervisor protection pin y selectable big or little endian byte ordering y high-speed interrupt controller e up to 248 external interrupts e 32 fully programmable priorities e multi-mode 8-bit interrupt port e four internal dma interrupts e separate, non-maskable interrupt pin e context switch in 750 ns typical
special environment 80960CF-30, -25, -16 271328 1 figure 1. 80960cf die photo 2
special environment 80960CF-30, -25, -16 32-bit high performance superscalar processor contents page 1.0 purpose 5 2.0 i960 cf processor overview 5 2.1 the c-series core 6 2.2 pipelined, burst bus 6 2.3 flexible dma controller 6 2.4 priority interrupt controller 6 2.5 instruction set summary 7 3.0 package information 8 3.1 package introduction 8 3.2 pin descriptions 8 3.3 80960cf pinout 14 3.4 mechanical data 18 3.5 package thermal specifications 20 3.6 stepping register information 21 3.7 suggested sources for 80960cf accessories 21 4.0 electrical specifications 22 4.1 absolute maximum ratings 22 4.2 operating conditions 22 4.3 recommended connections 22 4.4 dc specifications 23 4.5 ac specifications 24 5.0 reset, backoff and hold acknowledge 35 6.0 bus waveforms 36 contents page figures figure 1 80960cf die photo 2 figure 2 80960cf block diagram 5 figure 3 example pin description entry 8 figure 4a 80960cf pga pinout (view from top side) 16 figure 4b 80960cf pga pinout (view from bottom side) 17 figure 5 168-lead ceramic pga package dimensions 18 figure 6 80960cf pga package thermal characteristics 20 figure 7 measuring 80960cf pga case temperature 21 figure 8 register g0 21 figure 9 ac test load 30 figure 10a input and output clocks waveform 30 figure 10b clkin waveform 30 figure 11 output delay and float waveform 31 figure 12a input setup and hold waveform 31 figure 12b nmi , xint7:0 input setup and hold waveform 31 figure 13 hold acknowledge timings 32 figure 14 bus back-off (boff ) timings 32 3
contents page figure 15 relative timings waveforms 33 figure 16 output delay or hold vs load capacitance 33 figure 17 rise and fall time derating at highest operating temperature and minimum v cc 34 figure 18 i cc vs frequency and temperature 34 figure 19 cold reset waveform 36 figure 20 warm reset waveform 37 figure 21 entering the once state 38 figure 22a clock synchronization in the 2x clock mode 39 figure 22b clock synchronization in the 1x clock mode 39 figure 23 non-burst, non-pipelined requests without wait states 40 figure 24 non-burst, non-pipelined read request with wait states 41 figure 25 non-burst, non-pipelined write request with wait states 42 figure 26 burst, non-pipelined read request without wait states, 32-bit bus 43 figure 27 burst, non-pipelined read request with wait states, 32-bit bus 44 figure 28 burst, non-pipelined write request without wait states, 32-bit bus 45 figure 29 burst, non-pipelined write request with wait states, 32-bit bus 46 figure 30 burst, non-pipelined read request with wait states, 16-bit bus 47 contents page figure 31 burst, non-pipelined read request with wait states, 8-bit bus 48 figure 32 non-burst, pipelined read request without wait states, 32-bit bus 49 figure 33 non-burst, pipelined read request with wait states, 32-bit bus 50 figure 34 burst, pipelined read request without wait states, 32-bit bus 51 figure 35 burst, pipelined read requests with wait states, 32-bit bus 52 figure 36 burst, pipelined read requests with wait states, 16-bit bus 53 figure 37 burst, pipelined read requests with wait states, 8-bit bus 54 figure 38 using external ready 55 figure 39 terminating a burst with bterm 56 figure 40 boff functional timing 57 figure 41 hold functional timing 57 figure 42 dreq and dack functional timing 58 figure 43 eop functional timing 58 figure 44 terminal count functional timing 59 figure 45 fail functional timing 59 figure 46 a summary of aligned and unaligned transfers for little endian regions 60 figure 47 a summary of aligned and unaligned transfers for little endian regions (continued) 61 figure 48 idle bus operation 62 4
special environment 80960CF-30, -25, -16 1.0 purpose this document previews electrical characterizations of intel's i960 cf embedded microprocessor (avail- able in 33, 25 and 16 mhz). for a detailed descrip- tion of any i960 cf processor functional topiceoth- er than parametric performanceerefer to the latest i960 ca microprocessor reference manual (order no. 270710) and the i960 cf reference manual ad- dendum (order no. 272188). 2.0 i960 cf processor overview intel's i960 cf microprocessor is the performance follow-on product to the i960 ca processor. the i960 cf product is socket- and object code-compati- ble with the ca; this makes ca-to-cf design up- grades straightforward. the i960 cf processor's in- struction cache is 4 kbytes (ca device has 1 kbyte); cf data cache is 1 kbyte (ca device has no data cache). this extra cache on the cf product adds a significant performance boost over the ca. the 80960cf is object code compatible with the 32-bit 80960 core architecture while including special function register extensions to control on-chip pe- ripherals, and instruction set extensions to shift 64- bit operands and configure on-chip hardware. multi- ple 128-bit internal busses, on-chip instruction cach- ing and a sophisticated instruction scheduler allow the processor to sustain execution of two instruc- tions every clock, and peak at execution of three instructions per clock. a 32-bit demultiplexed and pipelined burst bus pro- vides a 132 mbyte/s bandwidth to a system's high- speed external memory sub-system. in addition, the 80960cf's on-chip caching of instructions, proce- dure context and critical program data substantially decouples system performance from the wait states associated with accesses to the system's slower, cost sensitive, main memory sub-system. the 80960cf bus controller also integrates full wait state and bus width control for highest system per- formance with minimal system design complexity. unaligned access and big endian byte order support reduces the cost of porting existing applications to the 80960cf. the processor also integrates four complete data- chaining dma channels and a high-speed interrupt controller on-chip. the dma channels perform: sin- gle-cycle or two-cycle transfers, data packing and unpacking, and data chaining. block transfers, in ad- dition to source or destination synchronized trans- fers, are provided. the interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (``latency'') time of 750 ns. 271328 2 figure 2. 80960cf block diagram 5
special environment 80960CF-30, -25, -16 2.1. the c-series core the c-series core is a very high performance micro- architectural implementation of the 80960 core ar- chitecture. the c-series core can sustain execution of two instructions per clock (66 mips at 33 mhz). to achieve this level of performance, intel has incor- porated state-of-the-art silicon technology and inno- vative microarchitectural constructs into the imple- mentation of the c-series core. factors that contrib- ute to the core's performance include: e parallel instruction decoding allows issue of up to three instructions per clock. e most instructions execute in a single clock. e parallel instruction decode allows sustained, simultaneous execution of two single-clock in- structions every clock cycle. e efficient instruction pipeline minimizes pipeline break losses. e register and resource scoreboarding allow simultaneous multi-clock instruction execution. e branch look-ahead and prediction allows many branches to execute with no pipeline break. e local register cache integrated on-chip caches call/return context. e two-way set associative, 4 kbyte integrated in- struction cache. e direct mapped, 1 kbyte data cache, write through, write allocate. e 1 kbyte integrated data ram sustains a four- word (128-bit) access every clock cycle. 2.2. pipelined, burst bus a 32-bit high performance bus controller interfaces the 80960cf to external memory and peripherals. the bus control unit features a maximum transfer rate of 132 mbytes per second (at 33 mhz). internal- ly programmable wait states and 16 separately con- figurable memory regions allow the processor to in- terface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. the bus controller's main features in- clude: e demultiplexed, burst bus to exploit most efficient dram access modes. e address pipelining to reduce memory cost while maintaining performance. e 32-, 16- and 8-bit modes for i/o interfacing ease. e full internal wait state generation to reduce sys- tem cost. e little and big endian support to ease application development. e unaligned access support for code portability. e three-deep request queue to decouple the bus from the core. 2.3. flexible dma controller a four channel dma controller provides high speed dma control for data transfers involving peripherals and memory. the dma provides advanced features such as data chaining, byte assembly and disassem- bly, and a high performance fly-by mode capable of transfer speed of up to 59 mbytes per second at 33 mhz. the dma controller features a performance and flexibility which is only possible by integrating the dma controller and the 80960cf core. 2.4. priority interrupt controller a programmable-priority interrupt controller man- ages up to 248 external sources through the 8-bit external interrupt port. the interrupt unit also han- dles the four internal sources from the dma control- ler, and a single non-maskable interrupt input. the 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered. interrupts in the 80960cf are prioritized and sig- naled within 270 ns of the request. if the interrupt is of higher priority than the processor priority, the con- text switch to the interrupt routine typically is com- plete in another 480 ns. the interrupt unit provides the mechanism for the low latency and high through- put interrupt service which is essential for embedded applications. 6
special environment 80960CF-30, -25, -16 2.5. instruction set summary the following table summarizes the 80960cf instruction set by logical groupings. see the i960 ca microproc- essor reference manual for a complete description of the instruction set. data arithmetic logical bit, bit field movement and byte load add and set bit store subtract not and clear bit move multiply and not not bit load address divide or alter bit remainder exclusive or scan for bit modulo not or span over bit shift or not extract * extended nor modify shift exclusive nor scan byte for equal extended not multiply nand extended divide add with carry subtract with carry rotate comparison branch call and return fault compare unconditional call conditional conditional branch call extended fault compare conditional call system synchronize compare and branch return faults increment compare and branch and link compare and branch decrement test condition code check bit debug processor atomic management modify trace modify atomic add controls process atomic modify mark controls force mark modify arithmetic controls * system control * dma control flush local registers note: instructions marked by ( * ) are 80960cf extensions to the 80960 instruction set. 7
special environment 80960CF-30, -25, -16 3.0 package information 3.1. package introduction this section describes the pins, pinouts and thermal characteristics for the 80960cf in the 168-pin ce- ramic pin grid array (pga) package. for complete package specifications and information, see the intel packaging outlines and dimensions guide (order no. 231369). 3.2. pin descriptions the 80960cf pins are described in this section. ta- ble 1 presents the legend for interpreting the pin de- scriptions in the following tables. pins associated with the 32-bit demultiplexed proc- essor bus are described in table 2. pins associated with basic processor configuration and control are described in table 3. pins associated with the 80960cf dma controller and interrupt unit are de- scribed in table 4. figure 3 provides an example pin description table entry. ``i/o'' signifies that data pins are input-output. ``s'' indicates pins are synchronous to pclk2:1. ``h(z)'' indicates that these pins float while the proc- essor bus is in a hold acknowledge state. ``r(z)'' indicates that the pins also float while reset is low. all pins float while the processor is in the once mode. table 1. pin description nomenclature symbol description i input only pin o output only pin i/o pin can be either an input or output - pins ``must be'' connected as described s(...) synchronous. inputs must meet setup and hold times relative to pclk2:1 for proper operation. all outputs are synchronous to pclk2:1. s(e) edge sensitive input s(l) level sensitive input a(...) asynchronous. inputs may be asynchronous to pclk2:1. a(e) edge sensitive input a(l) level sensitive input h(...) while the processor's bus is in the hold acknowledge or bus backoff state, the pin: h(1) is driven to v cc h(0) is driven to v ss h(z) floats h(q) continues to be a valid output r(...) while the processor's reset pin is low, the pin r(1) is driven to v cc r(0) is driven to v ss r(z) floats r(q) continues to be a valid output name type description d31:0 i/o data bus carries 32-, 16- or 8-bit data quantities depending on bus width configuration. the least significant bit of the data is carried on d0 and the most significant on d31. when s(l) the bus is configured for 8-bit data, the lower 8 data lines, d7:0 are used. for 16-bit bus h(z) widths, d15:0 are used. for 32-bit bus widths the full data bus is used. r(z) figure 3. example pin description entry 8
special environment 80960CF-30, -25, -16 table 2. 80960cf pin descriptioneexternal bus signals name type description a31:2 o address bus carries the physical address upper 30 bits. a31 is the most significant address bit and a2 is the least significant. during a bus access, a31:2 s identify all external addresses to word (4-byte) boundaries. the byte enable h(z) signals indicate the selected byte in each word. during burst accesses, a3 and a2 r(z) increment to indicate successive data cycles. d31:0 i / o data bus carries 32-, 16- or 8-bit data quantities depending on bus width configuration. the least significant bit of the data is carried on d0 and the most s(l) significant on d31. when the bus is configured for 8-bit data, the lower 8 data h(z) lines, d7:0 are used. for 16-bit bus widths, d15:0 are used. for 32-bit bus widths r(z) the full data bus is used. be3 o byte enables select which of the four bytes addressed by a31:2 are active during an access to a memory region configured for a 32-bit data-bus width. be3 be2 s applies to d31:24; be2 applies to d23:16; be1 applies to d15:8; and be0 applies be1 h(z) to d7:0. be0 r(1) 32-bit bus: be3 byte enable 3 enable d31:24 be2 byte enable 2 enable d23:16 be1 byte enable 1 enable d15:8 be0 byte enable 0 enable d7:0 for accesses to a memory region configured for a 16-bit data-bus width, the processor directly encodes be3 , be1 and be0 to provided bhe , a1 and ble respectively. 16-bit bus: be3 byte high enable (bhe ) enable d15:8 be2 not used (is driven high or low) be1 address bit 1 (a1) be0 byte low enable (ble ) enable d7:0 for accesses to a memory region configured for an 8-bit data bus width, the processor directly encodes be1 and be0 to provide a1 and a0 respectively. 8-bit bus: be3 not used (is driven high or low) be2 not used (is driven high or low) be1 address bit 1 (a1) be0 address bit 0 (a0) w/r o write/read is asserted for read requests and deasserted for write requests. the w/r signal changes in the same clock cycle as ads . it remains valid for the s entire access in non-pipelined regions. in pipelined regions, w/r is not h(z) guaranteed valid in the last cycle of a read access. r(0) ads o address strobe indicates valid address and the start of a new bus access. ads is asserted for the first clock of a bus access. s h(z) r(1) ready i ready is an input which signals the termination of a data transfer. ready is used to indicate that read data on the bus is valid, or that a write-data transfer has s(l) completed. the ready signal works in conjunction with the internally h(z) programmed wait-state generator. if ready is enabled in a region, the pin is r(z) sampled after the programmed number of wait-states has expired. if the ready pin is deasserted, wait states continue to be inserted until ready becomes asserted. this is true for the n rad ,n rdd ,n wad , and n wdd wait states. the n xda wait states cannot be extended. 9
special environment 80960CF-30, -25, -16 table 2. 80960cf pin descriptioneexternal bus signals (continued) name type description bterm i burst terminate ethe burst terminate signal breaks up a burst access and causes another address cycle to occur. the bterm signal works in conjunction s(l) with the internally programmed wait-state generator. if ready and bterm are h(z) enabled in a region, the bterm pin is sampled after the programmed number of r(z) wait states has expired. when bterm is asserted, a new ads signal is generated and the access is completed. the ready input is ignored when bterm is asserted. bterm must be externally synchronized to satisfy the bterm setup and hold times. wait o wait indicates internal wait state generator status. wait is asserted when wait states are being caused by the internal wait state generator and not by the s ready or bterm inputs. wait can be used to derive a write-data strobe. wait h(z) can also be thought of as a ready output that the processor provides when it is r(1) inserting wait states. blast o burst last indicates the last transfer in a bus access. blast is asserted in the last data transfer of burst and non-burst accesses after the wait state counter s reaches zero. blast remains asserted until the clock following the last cycle of h(z) the last data transfer of a bus access. if the ready or bterm input is used to r(0) extend wait states, the blast signal remains asserted until ready or bterm terminates the access. dt/r o data transmit/receive indicates direction for data transceivers. dt/r is used in conjunction with den to provide control for data transceivers attached to s the external bus. when dt/r is asserted, the signal indicates that the processor h(z) receives data. conversely, when deasserted, the processor sends data. dt/r r(0) changes only while den is high. den o data enable indicates data cycles in a bus request. den is asserted at the start of the bus request first data cycle and is deasserted at the end of the last s data cycle. den is used in conjunction with dt/r to provide control for data h(z) transceivers attached to the external bus. den remains asserted for sequential r(1) reads from pipelined memory regions. den is deasserted when dt/r changes. lock o bus lock indicates that an atomic read-modify-write operation is in progress. lock may be used to prevent external agents from accessing memory which is s currently involved in an atomic operation. lock is asserted in the first clock of an h(z) atomic operation, and deasserted in the clock cycle following the last bus access r(1) for the atomic operation. to allow the most flexibility for a memory system enforcement of locked accesses, the processor acknowledges a bus hold request when lock is asserted. the processor performs dma transfers while lock is active. hold i hold request signals that an external agent requests access to the external bus. the processor asserts holda after completing the current bus request. s(l) hold, holda and breq are used together to arbitrate access to the h(z) processor's external bus by external bus agents. r(z) boff i bus backoff ethe backoff pin, when asserted, suspends the current access and causes the bus pins to float. when deasserted, the ads signal is asserted on s(l) the next clock cycle and the access is resumed. h(z) r(z) 10
special environment 80960CF-30, -25, -16 table 2. 80960cf pin descriptioneexternal bus signals (continued) name type description holda o hold acknowledge indicates to a bus requestor that the processor has relinquished control of the external bus. when holda is asserted, the external s address bus, data bus and bus control signals are floated. hold, boff , holda h(1) and breq are used together to arbitrate access to the processor's external bus r(q) by external bus agents. since the processor grants hold requests and enters the hold acknowledge state even while reset is asserted, holda pin state is independent of the reset pin. breq o bus request is asserted when the bus controller has a request pending. breq can be used by external bus arbitration logic in conjunction with hold and s holda to determine when to return mastership of the external bus to the h(q) processor. r(0) d/c o data or code is asserted for a data request and deasserted for instruction requests. d/c has the same timing as w/r . s h(z) r(z) dma o dma access indicates whether the bus request was initiated by the dma controller. dma is asserted for any dma request. dma is deasserted for all other s requests. h(z) r(z) sup o supervisor access indicates whether the bus request is issued while in supervisor mode. sup is asserted when the request has supervisor privileges, and s is deasserted otherwise. sup can be used to isolate supervisor code and data h(z) structures from non-supervisor requests. r(z) table 3. 80960cf pin descriptioneprocessor control signals name type description reset i reset causes the chip to reset. when reset is asserted, all external signals return to the reset state. when reset is deasserted, initialization begins. when the 2-x clock a(l) mode is selected, reset must remain asserted for 16 pclk2:1 cycles before being h(z) deasserted in order to guarantee correct processor initialization. when the 1-x clock r(z) mode is selected, reset must remain asserted for 10,000 pclk2:1 cycles before n(z) being deasserted in order to guarantee correct initialization. the clkmode pin selects 1-x or 2-x input clock division of the clkin pin. the processor's hold acknowledge bus state functions while the chip is reset. if the processor's bus is in the hold acknowledge state when reset is asserted, the processor will internally reset, but maintains the hold acknowledge state on external pins until the hold request is removed. if a hold request is made while the processor is in the reset state, the processor bus grants holda and enters the hold acknowledge state. fail o fail indicates failure of the processor's self-test performed at initialization. when reset is deasserted and the processor begins initialization, the fail pin is asserted. s an internal self-test is performed as part of the initialization process. if this self-test h(q) passes, the fail pin is deasserted otherwise it remains asserted. the fail pin is r(0) reasserted while the processor performs an external bus self-confidence test. if this self-test passes, the processor deasserts the fail pin and branches to the user's initialization routine; otherwise the fail pin remains asserted. internal self-test and the use of the fail pin can be disabled with the stest pin. 11
special environment 80960CF-30, -25, -16 table 3. 80960cf pin descriptioneprocessor control signals (continued) name type description stest i self test causes the processor's internal self-test feature to be enabled or disabled at initialization. stest is read on the rising edge of reset . when asserted, s(l) the processor's internal self-test and external bus confidence tests are performed h(z) during processor initialization. when deasserted, only the external bus confidence r(z) tests are performed during initialization. once i on circuit emulation causes all outputs to be floated when asserted. once is continuously sampled while reset is low, and is latched on the rising edge of a(l) reset . to place the processor in the once state: h(z) (1) assert reset and once (order does not matter) r(z) (2) wait for at least 16 clkin periods in 2-x mode, or 10,000 clkin periods in 1-x mode, after v cc and clkin are within operating specifications (3) deassert reset (4) wait at least 32 clkin periods (the processor is now latched in the once state as long as reset is high.) to exit the once state, bring v cc and clkin to operating conditions, then assert reset and bring once high prior to deasserting reset . clkin must operate within the specified operating conditions of the processor until step 4 above is completed. the clkin may then be changed to dc to achieve the lowest possible once mode leakage current. once can be used by emulator products or for board testers to effectively make an installed processor transparent in the board. clkin i clock input is an input for the external clock needed to run the processor. the external clock is internally divided as prescribed by the clkmode pin to produce a(e) pclk2:1. h(z) r(z) clkmode i clock mode selects the division factor applied to the external clock input (clkin). when clkmode is high, clkin is divided by one to create pclk2:1 and the a(l) processor's internal clock. when clkmode is low, clkin is divided by two to create h(z) pclk2:1 and the processor's internal clock. clkmode should be tied high or low in r(z) a system, as the clock mode is not latched by the processor. if left unconnected, the processor internally pulls the clkmode pin low, enabling the 2-x clock mode. pclk2 o processor output clocks provide a timing reference for all inputs and outputs of the processor. all inputs and output timings are specified in relation to pclk1 s pclk2 and pclk1. pclk2 and pclk1 are identical signals. two output pins are h(q) provided to allow flexibility in the system's allocation of capacitive loading on the r(q) clock. pclk2:1 may also be connected at the processor to form a single clock signal. v ss e ground connections consist of 24 pins which must be connected externally to a v ss board plane. v cc e power connections consist of 24 pins which must be connected externally to a v cc board plane. v ccpll ev ccpll is a separate v cc supply pin for the phase lock loop used in 1x clock mode. connecting a simple low pass filter to v ccpll may help reduce clock jitter (t cp )in noisy environments. otherwise, v ccpll should be connected to v cc . n/c e no connect pins must not be connected in a system. 12
special environment 80960CF-30, -25, -16 table 4. 80960cf pin descriptionedma and interrupt unit control signals name type description dreq3 i dma request causes a dma transfer to be requested. each of the four signals request a transfer on a single channel. dreq0 requests channel 0, dreq1 requests dreq2 a(l) channel 1, etc. when two or more channels are requested simultaneously, the dreq1 h(z) channel with the highest priority is serviced first. channel priority mode is dreq0 r(z) programmable. dack3 o dma acknowledge indicates that a dma transfer is being executed. each of the four signals acknowledge a transfer for a single channel. dack0 acknowledges dack2 s channel 0, dack1 acknowledges channel 1, etc. dack3:0 are asserted when the dack1 h(1) requesting device of a dma is accessed. dack0 r(1) eop3/tc3 i / o end of process/terminal count can be programmed as either an input (eop3:0 ) or as an output (tc3:0 ), but not both. each pin is individually eop2/tc2 a(l) programmable. when programmed as an input, eopx causes the termination of a eop1/tc1 h(z/q) current dma transfer for the channel corresponding to the eopx pin. eop0 eop0/tc0 r(z) corresponds to channel 0, eop1 corresponds to channel 1, etc. when a channel is configured for source and destination chaining, the eop pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred. eop3:0 are asynchronous inputs. when programmed as an output, the channel's tcx pin indicates that the channel byte count has reached 0 and a dma has terminated. tcx is driven with the same timing as dackx during the last dma transfer for a buffer. if the last bus request is executed as multiple bus accesses, tcx remains asserted for the entire bus request. xint7 i external interrupt pins cause interrupts to be requested. these pins can be configured in three modes. xint6 a(e/l) in dedicated mode, each pin is a dedicated external interrupt source. dedicated xint5 h(z) inputs can be individually programmed to be level (low) or edge (falling) activated. xint4 r(z) in expanded mode, the 8 pins act together as an 8-bit vectored interrupt source. the xint3 interrupt pins in this mode are level activated. since the interrupt pins are active low, xint2 the vector number requested is the one's complement of the positive logic value xint1 place on the port. this eliminates glue logic to interface to combinational priority xint0 encoders which output negative logic. in mixed mode, xint7:5 are dedicated sources and xint4:0 act as the 5 most significant bits of an expanded mode vector. the least significant bits are set to 010 internally. nmi i non-maskable interrupt causes a non-maskable interrupt event to occur. nmi is the highest priority interrupt recognized. nmi is an edge (falling) activated a(e) source. h(z) r(z) 13
special environment 80960CF-30, -25, -16 3.3. 80960cf pinout 3.3.1 80960cf pga pinout tables 5 and 6 list the 80960cf pin names with package location. figure 4-a depicts the complete 80960cf pinout as viewed from the top side of the component (i.e., pins facing down). figure 4b shows the complete 80960cf pinout as viewed from the pin-side of the package (i.e., pins facing up). see section 4.0, electrical specifications for specifica- tions and recommended connections. table 5. pga pin name with package location (signal order) address bus data bus bus control processor control i/o name location name location name location name location name location a31 s15 d31 r03 be3 s05 reset a16 dreq3 a07 a30 q13 d30 q05 be2 s06 dreq2 b06 a29 r14 d29 s02 be1 s07 fail a02 dreq1 a06 a28 q14 d28 q04 be0 r09 dreq0 b05 a27 s16 d27 r02 stestb02 a26 r15 d26 q03 w/r s10 dack3 a10 a25 s17 d25 s01 once c03 dack2 a09 a24 q15 d24 r01 ads r06 dack1 a08 a23 r16 d23 q02 cklin c13 dack0 b08 a22 r17 d22 p03 ready s03 clkmode c14 a21 q16 d21 q01 bterm r04 pclk1 b14 eop /tc0 a11 a20 p15 d20 p02 pclk2 b13 eop /tc1 a12 a19 p16 d19 p01 wait s12 eop /tc2 a13 a18 q17 d18 n02 blast s08 v ss eop /tc3 a14 a17 p17 d17 n01 location a16 n16 d16m01 dt/r s11 c07, c08, c09, xint7 c17 c10, c11, c12, a15 n17 d15 l01 den s09 xint6 c16 f15, g03, g15, a14 m17 d14 l02 xint5 b17 h03, h15, j03, j15, k03, k15, a13 l16 d13 k01 lock s14 xint4 c15 l03, l15, m03, a12 l17 d12 j01 xint3 b16 m15, q07, q08, q09, q10, q11 a11 k17 d11 h01 hold r05 xint2 a17 a10 j17 d10 h02 holda s04 v cc xint1 a15 a9 h17 d9 g01 breq r13 location xint0 b15 a8 g17 d8 f01 b07, b09, b11, b12, c06, a7 g16 d7 e01 d/c s13 nmi d15 e15, f03, f16, a6 f17 d6 f02 dma r12 g02, h16, j02, j16, k02, k16, m02, a5 e17 d5 d01 sup q12 m16, n03, n15, a4 e16 d4 e02 q06, r07, r08, r10, r11 v ccpll b10 a3 d17 d3 c01 boff b01 no connect a2 d16 d2 d02 location d1 c02 a01, a03, a04, a05, b03, b04, c04, c05, d03 d0 e03 14
special environment 80960CF-30, -25, -16 table 6. pga pin name with package location (pin order) address bus data bus bus control processor control i/o location name location name location name location name location name a01 nc c01 d3 g01 d9 m01 d16 r01 d24 a02 fail c02 d1 g02 v cc m02 v cc r02 d27 a03 nc c03 once g03 v ss m03v ss r03 d31 a04 nc c04 nc g15 v ss m15v ss r04bterm a05 nc c05 nc g16 a7 m16 v cc r05 hold a06 dreq1 c06 v cc g17 a8 m17a14 r06 ads a07 dreq3 c07 v ss r07 v cc a08 dack1 c08 v ss h01 d11 n01d17 r08 v cc a09 dack2 c09 v ss h02 d10 n02d18 r09 be0 a10 dack3 c10 v ss h03 v ss n03v cc r10 v cc a11 eop/tc0 c11 v ss h15 v ss n15v cc r11 v cc a12 eop/tc1 c12 v ss h16 v cc n16 a16 r12 dma a13 eop/tc2 c13 clkin h17 a9 n17 a15 r13 breq a14 eop/tc3 c14 clkmode r14 a29 a15 xint1 c15 xint4 j01 d12 p01 d19 r15 a26 a16 reset c16 xint6 j02 v cc p02 d20 r16 a23 a17 xint2 c17 xint7 j03 v ss p03 d22 r17 a22 j15 v ss p15 a20 b01 boff d01 d5 j16 v cc p16 a19 s01 d25 b02 stest d02 d2 j17 a10 p17 a17 s02 d29 b03 nc d03 nc s03 ready b04 nc d15 nmi k01 d13 q01d21 s04 holda b05 dreq0 d16 a2 k02 v cc q02d23 s05 be3 b06 dreq2 d17 a3 k03 v ss q03d26 s06 be2 b07 v cc k15 v ss q04d28 s07 be1 b08 dack0 e01 d7 k16 v cc q05d30 s08 blast b09 v cc e02 d4 k17 a11 q06v cc s09 den b10 v ccpll e03 d0 q07 v ss s10 w/r b11 v cc e15 v cc l01 d15 q08 v ss s11dt/r b12 v cc e16 a4 l02 d14 q09 v ss s12 wait b13 pclk2 e17 a5 l03 v ss q10 v ss s13 d/c b14 pclk1 l15 v ss q11 v ss s14 lock b15 xint0 f01 d8 l16 a13 q12 sup s15 a31 b16 xint3 f02 d6 l17 a12 q13a30 s16 a27 b17 xint5 f03 v cc q14a28 s17 a25 f15 v ss q15a24 f16 v cc q16a21 f17 a6 q17a18 15
special environment 80960CF-30, -25, -16 271328 3 figure 4a. 80960cf pga pinout (view from top side) 16
special environment 80960CF-30, -25, -16 271328 4 figure 4b. 80960cf pga pinout (view from bottom side) 17
special environment 80960CF-30, -25, -16 3.4. mechanical data 3.4.1 ceramic pga package 271328 5 family: ceramic pin grid array package symbol millimeters inches min max notes min max notes a 3.56 4.57 0.140 0.180 a 1 0.64 1.14 solid lid 0.025 0.045 solid lid a 2 23 0.30 solid lid 0.110 0.140 solid lid a 3 1.14 1.40 0.045 0.055 b 0.43 0.51 0.017 0.020 d 44.07 44.83 1.735 1.765 d 1 40.51 40.77 1.595 1.605 e 1 2.29 2.79 0.090 0.110 l 2.54 3.30 0.100 0.130 n 168 168 s 1 1.52 2.54 0.060 0.100 issue iws rev x 7/15/88 figure 5. 168-lead ceramic pga package dimensions 18
special environment 80960CF-30, -25, -16 table 7. ceramic pga package dimension symbols letter or description of dimensions symbol a distance from seating plane to highest point of body a 1 distance between seating plane and base plane (lid) a 2 distance from base plane to highest point of body a 3 distance from seating plane to bottom of body b diameter of terminal lead pin d largest overall package dimension of length d 1 a body length dimension, outer lead center to outer lead center e 1 linear spacing between true lead position centerlines l distance from seating plane to end of lead s 1 other body dimension, outer lead center to edge of body notes: 1. controlling dimension: millimeter. 2. dimension ``e 1 '' (``e'') is non-cumulative. 3. seating plane (standoff) is defined by p.c. board hole size: 0.0415 0.0430 inch. 4. dimensions ``b'', ``b 1 '' and ``c'' are nominal. 5. details of pin 1 identifier are optional. 19
special environment 80960CF-30, -25, -16 3.5. package thermal specifications the 80960cf is specified for operation when t c (the case temperature) is within the range of b 40 c a 110 c. t c may be measured in any envi- ronment to determine whether the 80960cf is within specified operating range. the case temperature is measured at the center of the top surface, opposite the pins. refer to figure 7. t a (the ambient temperature) can be calculated from i ca (thermal resistance from case to ambient) with the following equation: t a e t c b p * i ca table 8 shows the maximum t a allowable (without exceeding t c ) at various airflows and operating fre- quencies (f pclk ). note that t a is greatly improved by attaching fins or a heat sink to the package. p (the maximum power consumption) is calculated by using the typical i cc as tabulated in section 4.4, dc specifications , and v cc of 5v. table 8. maximum t a at various airflows in c (pga package only) airflow-ft/min (m/sec) f pclk 0 200 400 600 800 1000 (mhz) (0) (1.01) (2.03) (3.04) (4.06) (5.07) t a 33 38 57 74 76 81 84 with 25 50 65 79 81 85 87 heat sink * 16 63 74 84 86 89 90 t a 33 18 33 47 57 66 67 without 25 34 46 57 65 72 74 heat sink 16 51 60 68 74 80 81 * 0.285 high unidirectional heat sink (al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). pga thermal resistancee c/watt parameter airfloweft./min (m/sec) 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.07) (4.06) (5.07) i junction-to-case (case measured 1.5 1.5 1.5 1.5 1.5 1.5 as shown in figure 7) i case-to-ambient 17 14 11 9 7.1 6.6 (no heatsink) i case-to-ambient (with unidirectional) 13 9 5.5 5.0 3.9 3.4 heatsink) * notes: 1. this table applies to 80960cf pga plugged into socket or soldered directly into board. 2. i ja e i jc a i ca . 3. i j-cap e 4 c/w (approx.) i j-pin e 4 c/w (inner pins) (approx.) i j-pin e 8 c/w (outer pins) (approx.) * 0.285 high unidirectional heat sink (al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). 271328 6 figure 6. 80960cf pga package thermal characteristics 20
special environment 80960CF-30, -25, -16 271328 7 figure 7. measuring 80960cf pga case temperature 3.6 stepping register information upon reset, register g0 contains die stepping in- formation. the following figure shows how g0 is configured. the most significant byte contains an ascii 0. the upper middle byte contains an ascii c. the lower middle byte contains an ascii f. the least significant byte contains the stepping number in ascii. g0 retains this information until it is written over by the user program. table 9 contains a cross reference of the number in the least significant byte of register g0 to the die stepping number. ascii 00 43 46 stepping number decimal 0 c f stepping number msb lsb figure 8. register g0 table 9. die stepping cross reference g0 least die stepping significant byte 01 a 02 b 03 c 04 d 05 e 3.7 suggested sources for 80960cf accessories the following are some suggested sources of ac- cessories for the 80960cf. they are neither an endorsement of any kind, nor a warranty of the performance of any of the listed products and/or companies. sockets 1. 3m textool test and interconnection products department p.o. box 2963 austin, tx 78769-2963 2. augat, inc. interconnection products group 33 perry avenue p.o. box 779 attleboro, ma 02703 (508) 222-2202 3. concept manufacturing inc. (decoupling sockets) 43024 christy street fremont, ca 94538 (415) 651-3804 heat sinks/fins 1. thermalloy, inc. 2021 west valley view lane dallas, tx 75381-0839 (214) 243-4321 2. e g & g division 60 audubon road wakefield, ma 01880 (617) 245-5900 21
special environment 80960CF-30, -25, -16 4.0 electrical specifications 4.1 absolute maximum ratings parameter maximum rating storage temperature b 65 cto a 150 c case temperature under bias (2) b 40 cto a 125 c supply voltage wrt. v ss b 0.5v to a 6.5v voltage on other pins wrt v ss b 0.5v to v cc a 0.5v notice: this data sheet contains information on products in the sampling and initial production phases of development. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. 4.2. operating conditions operating conditions (80960cf-33, -25, -16) symbol parameter min max units notes v cc supply voltage 80960CF-30 4.75 5.25 80960cf-25 4.50 5.50 v 80960cf-16 4.50 5.50 f clk2x input clock frequency (2-x mode) 80960CF-30 0 60.6 mhz 80960cf-25 0 50 mhz 80960cf-16 0 32 mhz f clk1x input clock frequency (1-x mode) 80960CF-30 8 30.3 mhz 80960cf-25 8 25 mhz (1) 80960cf-16 8 16 mhz t c case temperature under bias pga package b 40 a 110 c 80960CF-30, -25, -16 notes: (1) when in the 1-x input clock mode, clkin is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 mhz for proper processor operation. however, in the 1-x mode, clkin may still be stopped when the processor either is in a reset condition or is reset. if clkin is stopped, the specified reset low time must be provided once clkin restarts and has stabilized. (2) case temperatures are ``instant on''. 4.3 recommended connections power and ground connections must be made to multiple v cc and v ss (gnd) pins. every 80960cf- based circuit board should include power (v cc ) and ground (v ss ) planes for power distribution. every v cc pin must be connected to the power plane, and every v ss pin must be connected to the ground plane. pins identified as ``n.c.'' must not be con- nected in the system. liberal decoupling capacitance should be placed near the 80960cf. the processor can cause tran- sient power surges when its numerous output buff- ers transition, particularly when connected to large capacitive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. inductance can be reduced by shortening board traces between the processor and decoupling capacitors as much as possible. capacitors specifi- cally designed for pga packages will offer the low- est possible inductance. for reliable operation, always connect unused in- puts to an appropriate signal level. in particular, any unused interrupt (xint , nmi ) or dma (dreq ) input should be connected to v cc through a pull-up resis- tor, as should bterm if not used. pull-up resistors should be in the range of 20 k x for each pin tied high. if ready or hold are not used, the unused input should be connected to ground. n.c. pins must always remain unconnected. refer to the i960 ca microprocessor reference manual for more information. 22
special environment 80960CF-30, -25, -16 4.4. dc specifications dc characteristics (80960CF-30, -25, -16 under the conditions described in section 4.2, operating conditions .) symbol parameter min max units notes v il input low voltage for all pins except reset b 0.3 0.8 v v ih input high voltage for all pins except reset 2.0 v cc a 0.3 v v ol output low voltage 0.45 v i ol e 5ma v oh output high voltage i oh eb 1ma 2.4 v i oh eb 200 m av cc b 0.5 v v ilr input low voltage for reset b 0.3 1.5 v v ihr input high voltage for reset 3.5 v cc a 0.3 v i li1 input leakage current for each pin except : bterm , once , dreq3:0 , stest, eop3:0 /tc3:0 , nmi , xint7:0 , ready , hold, boff , clkmode g 15 m a0v s v in s v cc (1) i li2 input leakage current for: bterm , once , dreq3:0 , stest, eop3:0 /tc3:0 , nmi , xint7:0 , boff 0 b 325 m av in e 0.45v (2) i li3 input leakage current for: ready , hold, clkmode 0 500 m av in e 2.4v (3) i lo output leakage current g 15 m a 0.45v s v out s v cc i cc supply current (80960CF-30) i cc max 1150 ma (4) i cc typ 960 (5) i cc supply current (80960cf-25) i cc max 950 ma (4) i cc typ 775 (5) i cc supply current (80960cf-16) i cc max 750 ma (4) i cc typ 575 (5) i once once-mode supply current 150 ma c in input capacitance for: clkin, reset , once , ready , hold, dreq3:0 , boff xint7:0 , nmi , bterm , clkmode 0 12 pf f c e 1 mhz c out output capacitance of each output pin 12 pf f c e 1 mhz, (6) c i/o i/o pin capacitance 12 pf f c e 1 mhz notes: (1) no pull-up or pull-down. (2) these pins have internal pullup resistors. (3) these pins have internal pulldown resistors. (4) measured at worst case frequency, v cc and temperature, with device operating and outputs loaded to the test conditions described in section 4.5.1, ac test conditions. (5) i cc typical is not tested. (6) output capacitance is the capacitive load of a floating output. (7) clkmode pin has a pulldown resistor only when once pin is deasserted. 23
special environment 80960CF-30, -25, -16 4.5 ac specifications ac characteristics e 80960CF-30 (80960CF-30 only, under the conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) see notes which follow this table. symbol parameter min max units notes input clock (10) t f clkin frequency 0 60.6 mhz (1) t c clkin period in 1-x mode (f clk1x ) 33 125 ns (1,12) in 2-x mode (f clk2x ) 16.5 % ns (1) t cs clkin period stability in 1-x mode (f clk1x ) g 0.1% d (1,13) t ch clkin high time in 1-x mode (f clk1x ) 6 62.5 ns (1,12) in 2-x mode (f clk2x )6 % ns (1) t cl clkin low time in 1-x mode (f clk1x ) 6 62.5 ns (1,12) in 2-x mode (f clk2x )6 % ns (1) t cr clkin rise time 0 6 ns (1) t cf clkin fall time 0 6 ns (1) output clocks (9) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) b 2 2 ns (1,3,13,14) in 2-x mode (f clk2x ) 2 25 ns (1,3) t pclk2:1 period in 1-x mode (f clk1x )t c ns (1,13) in 2-x mode (f clk2x )2t c ns (1,3) t ph pclk2:1 high time (t/2) b 2 t/2 ns (1,13) t pl pclk2:1 low time (t/2) b 2 t/2 ns (1,13) t pr pclk2:1 rise time 1 4 ns (1,3) t pf pclk2:1 fall time 1 4 ns (1,3) synchronous outputs (10) t ov output valid delay, output hold (6, 11) t oh t ov1 ,t oh1 a31:2 3 14 ns t ov2 ,t oh2 be3:0 316ns t ov3 ,t oh3 ads 618ns t ov4 ,t oh4 w/r 318ns t ov5 ,t oh5 d/c , sup , dma 416ns t ov6 ,t oh6 blast , wait 516ns t ov7 ,t oh7 den 316ns t ov8 ,t oh8 holda, breq 4 16 ns t ov9 ,t oh9 lock 416ns t ov10 ,t oh10 dack3:0 418ns t ov11 ,t oh11 d31:0 3 16 ns t ov12 ,t oh12 dt/r t/2 a 3 t/2 a 14 ns t ov13 ,t oh13 fail 2 14 ns (6, 11) t ov14 ,t oh14 eop /tc3:0 318ns t of output float for all outputs 3 22 ns (6) synchronous inputs (10) t is input setup t is1 d31:0 3 ns (1,11) t is2 boff 17 ns (1,11) t is3 bterm /ready 7 ns (1,11) t is4 hold 7 ns (1,11) t ih input hold t ih1 d31:0 5 ns (1,11) t ih2 boff 5 ns (1,11) t ih3 bterm /ready 2 ns (1,11) t ih4 hold 3 ns (1,11) 24
special environment 80960CF-30, -25, -16 ac characteristics e 80960CF-30 (80960CF-30 only, under the conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) see notes which follow this table. (continued) symbol parameter min max units notes relative output timings (9,7) t avsh1 a31:2 valid to ads rising t b 4t a 4ns t avsh2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t b 6t a 6ns t avel1 a31:2 valid to den falling t b 4t a 4ns t avel2 be3:0 , w/r , sup , inst , dma , dack3:0 valid to den falling t b 6t a 6ns t nlqv wait falling to output data valid g 6ns t dvnh output data valid to wait rising n * t b 6n * t a 6 ns (4) t nlnh wait falling to wait rising n * t g 4 ns (4) t nhqx output data hold after wait rising (n a 1) * t b 6(n a 1) * t a 6 ns (5) t ehtv dt/r hold after den high t/2 b 6 % ns (6) t tvel dt/r valid to den falling t/2 b 4 t/2 a 4 ns (7) relative input timings (7) t is5 reset input setup (2x clock mode) 6 ns (14) t ih5 reset input hold (2x clock mode) 5 ns (14) t is6 dreq3:0 input setup 12 ns (8) t ih6 dreq3:0 input hold 7 ns (8) t is7 xint7:0 , nmi input setup 7 ns (8) t ih7 xint7:0 , nmi input hold 3 ns (8) t is8 reset input setup (1x clock mode) 3 ns (15) t ih8 reset input hold (1x clock mode) t/4 a 1 ns (15) notes: 1. see section 4.5.2, ac timing waveforms for waveforms and definitions. 2. see figure 22 for capacitive derating information for output delays and hold times. 3. see figure 23 for capacitive derating information for rise and fall times. 4. where n is the number of n rad ,n rdd ,n wad ,orn wdd wait states that are programmed in the bus controller region table. when there are no wait states in an access, wait never goes active. 5. n e number of wait states inserted with ready . 6. output data and/or dt/r may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. see notes 1, 2 and 3. 8. since asynchronous inputs are synchronized internally by the 80960cf they have no required setup or hold times in order to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1 the setup times shown must be met. asynchronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor. 9. these specifications are guaranteed by the processor. 10. these specifications must be met by the system for proper operation of the processor. 11. this timing is dependent upon the loading of pclk2:1. use the derating curves of section 4.5.3 to adjust the timing for pclk2:1 loading. 12. in the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode. 13. when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than g 0.1% between adjacent cycles. 14. in 2x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the falling edge of the clkin. (see figure 28a.) 15. in 1x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must be deasserted while clkin is high and meet setup and hold times to the rising edge of the clkin. (see figure 28b.) 25
special environment 80960CF-30, -25, -16 ac characteristics e 80960cf-25 (80960cf-25 only, under the conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) symbol parameter min max units notes input clock (10) t f clkin frequency 0 50 mhz (1) t c clkin period in 1-x mode (f clk1x ) 40 125 ns (1,12) in 2-x mode (f clk2x )20 % ns (1) t cs clkin period stability in 1-x mode (f clk1x ) g 0.1% d (1,13) t ch clkin high time in 1-x mode (f clk1x ) 8 62.5 ns (1,12) in 2-x mode (f clk2x )8 % ns (1) t cl clkin low time in 1-x mode (f clk1x ) 8 62.5 ns (1,12) in 2-x mode (f clk2x )8 % ns (1) t cr clkin rise time 0 6 ns (1) t cf clkin fall time 0 6 ns (1) output clocks (9) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) b 2 2 ns (1,3,13,14) in 2-x mode (f clk2x ) 2 25 ns (1,3) t pclk2:1 period in 1-x mode (f clk1x )t c ns (1,13) in 2-x mode (f clk2x )2t c ns (1,3) t ph pclk2:1 high time (t/2) b 3 t/2 ns (1,13) t pl pclk2:1 low time (t/2) b 3 t/2 ns (1,13) t pr pclk2:1 rise time 1 4 ns (1,3) t pf pclk2:1 fall time 1 4 ns (1,3) synchronous outputs (10) t ov output valid delay, output hold (6, 11) t oh t ov1 ,t oh1 a31:2 3 16 ns t ov2 ,t oh2 be3:0 318ns t ov3 ,t oh3 ads 620ns t ov4 ,t oh4 w/r 320ns t ov5 ,t oh5 d/c ,sup ,dma 418ns t ov6 ,t oh6 blast , wait 518ns t ov7 ,t oh7 den 318ns t ov8 ,t oh8 holda, breq 4 18 ns t ov9 ,t oh9 lock 418ns t ov10 ,t oh10 dack3:0 420ns t ov11 ,t oh11 d31:0 3 18 ns t ov12 ,t oh12 dt/r t/2 a 3 t/2 a 16 ns t ov13 ,t oh13 fail 216ns t ov14 ,t oh14 eop3:0 /tc3:0 3 20 ns (6, 11) t of output float for all outputs 3 22 ns (6) synchronous inputs (10) t is input setup t is1 d31:0 5 ns (1,11) t is2 boff 19 ns (1,11) t is3 bterm /ready 9 ns (1,11) t is4 hold 9 ns (1,11) t ih input hold t ih1 d31:0 5 ns (1,11) t ih2 boff 7 ns (1,11) t ih3 bterm /ready 2 ns (1,11) t ih4 hold 5 ns (1,11) 26
special environment 80960CF-30, -25, -16 ac characteristics e 80960cf-25 (80960cf-25 only, under the conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) (continued) symbol parameter min max units notes relative output timings (9,7) t avsh1 a31:2 valid to ads rising t b 4t a 4ns t avsh2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t b 6t a 6ns t avel1 a31:2 valid to den falling t b 4t a 4ns t avel2 be3:0 , w/r , sup , inst , dma , dack3:0 valid to den falling t b 6t a 6ns t nlqv wait falling to output data valid g 6ns t dvnh output data valid to wait rising n * t b 6n * t a 6 ns (4) t nlnh wait falling to wait rising n * t g 4 ns (4) t nhqx output data hold after wait rising (n a 1) * t b 6(n a 1) * t a 6 ns (5) t ehtv dt/r hold after den high t/2 b 6 % ns (6) t tvel dt/r valid to den falling t/2 b 4 t/2 a 4 ns (7) relative input timings (7) t is5 reset input setup (2x clock mode 8 ns (14) t ih5 reset input hold (2x clock mode) 7 ns (14) t is6 dreq3:0 input setup 14 ns (8) t ih6 dreq3:0 input hold 9 ns (8) t is7 xint7:0 , nmi input setup 9 ns (8) t ih7 xint7:0 , nmi input hold 5 ns (8) t is8 reset input setup (1x clock mode) 3 ns (15) t ih8 reset input hold (1x clock mode) t/4 a 1 ns (15) notes: (1) see section 4.5.2, ac timing waveforms for waveforms and definitions. (2) see figure 22 for capacitive derating information for output delays and hold times. (3) see figure 23 for capacitive derating information for rise and fall times. (4) where n is the number of n rad ,n rdd ,n wad ,orn wdd wait states that are programmed in the bus controller region table. when there are no wait states in an access, wait never goes active. (5) n e number of wait states inserted with ready . (6) output data and/or dt/r may be driven indefinitely following a cycle if there is no subsequent bus activity. (7) see notes 1, 2 and 3. (8) since asynchronous inputs are synchronized internally by the 80960cf they have no required setup or hold times in order to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1 the setup times shown must be met. asynchronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor. (9) these specifications are guaranteed by the processor. (10) these specifications must be met by the system for proper operation of the processor. (11) this timing is dependent upon the loading of pclk2:1. use the derating curves of section 4.5.3 to adjust the timing for pclk2:1 loading. (12) in the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode. (13) when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than g 0.1% between adjacent cycles. (14) in 2x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the falling edge of the clkin. (see figure 28a.) (15) in 1x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must be deasserted while clkin is high and meet setup and hold times to the rising edge of the clkin. (see figure 28b.) 27
special environment 80960CF-30, -25, -16 ac characteristics e 80960cf-16 (80960cf-16 only, under the conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) (continued) symbol parameter min max units notes input clock (10) t f clkin frequency 0 32 mhz (1) t c clkin period in 1-x mode (f clk1x ) 62.5 125 ns (1,12) in 2-x mode (f clk2x ) 31.25 % ns (1) t cs clkin period stability in 1-x mode (f clk1x ) g 0.1% d (1,13) t ch clkin high time in 1-x mode (f clk1x ) 10 62.5 ns (1,12) in 2-x mode (f clk2x )10 % ns (1) t cl clkin low time in 1-x mode (f clk1x ) 10 62.5 ns (1,12) in 2-x mode (f clk2x )10 % ns (1) t cr clkin rise time 0 6 ns (1) t cf clkin fall time 0 6 ns (1) output clocks (9) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) b 2 2 ns (1,3,13,14) in 2-x mode (f clk2x ) 2 25 ns (1,3) t pclk2:1 period in 1-x mode (f clk1x )t c ns (1,13) in 2-x mode (f clk2x )2t c ns (1,3) t ph pclk2:1 high time (t/2) b 4 t/2 ns (1,13) t pl pclk2:1 low time (t/2) b 4 t/2 ns (1,13) t pr pclk2:1 rise time 1 4 ns (1,3) t pf pclk2:1 fall time 1 4 ns (1,3) synchronous outputs (10) t ov output valid delay, output hold (6, 11) t oh t ov1 ,t oh1 a31:2 3 18 ns t ov2 ,t oh2 be3:0 320ns t ov3 ,t oh3 ads 622ns t ov4 ,t oh4 w/r 322ns t ov5 ,t oh5 d/c , sup , dma 420ns t ov6 ,t oh6 blast , wait 520ns t ov7 ,t oh7 den 320ns t ov8 ,t oh8 holda, breq 4 20 ns t ov9 ,t oh9 lock 420ns t ov10 ,t oh10 dack3:0 422ns t ov11 ,t oh11 d31:0 3 20 ns t ov12 ,t oh12 dt/r t/2 a 3 t/2 a 18 ns t ov13 ,t oh13 fail 218ns t ov14 ,t oh14 eop3:0 /tc3:0 3 22 ns (6, 11) t of output float for all outputs 3 22 ns (6) synchronous inputs (10) t is input setup t is1 d31:0 5 ns (1,11) t is2 boff 21 ns (1,11) t is3 bterm /ready 9 ns (1,11) t is4 hold 9 ns (1,11) t ih input hold t ih1 d31:0 5 ns (1,11) t ih2 boff 7 ns (1,11) t ih3 bterm /ready 2 ns (1,11) t ih4 hold 5 ns (1,11) 28
special environment 80960CF-30, -25, -16 ac characteristics e 80960cf-16 (80960cf-16 only, under the conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) (continued) symbol parameter min max units notes relative output timings (9,7) t avsh1 a31:2 valid to ads rising t b 4t a 4ns t avsh2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t b 6t a 6ns t avel1 a31:2 valid to den falling t b 6t a 6ns t avel2 be3:0 , w/r , sup , inst , dma , dack3:0 valid to den falling t b 6t a 6ns t nlqv wait falling to output data valid g 6ns t dvnh output data valid to wait rising n * t b 6n * t a 6 ns (4) t nlnh wait falling to wait rising n * t g 4 ns (4) t nhqx output data hold after wait rising (n a 1) * t b 6(n a 1) * t a 6 ns (5) t ehtv dt/r hold after den high t/2 b 6 % ns (6) t tvel dt/r valid to den falling t/2 b 4 t/2 a 4 ns (7) relative input timings (7) t is5 reset input setup (2x clock mode) 10 ns (14) t ih5 reset input hold (2x clock mode) 9 ns (14) t is6 dreq3:0 input setup 16 ns (8) t ih6 dreq3:0 input hold 11 ns (8) t is7 xint7:0 , nmi input setup 9 ns (8) t ih7 xint7:0 , nmi input hold 5 ns (8) t is8 reset input setup (1x clock mode) 3 ns (15) t ih8 reset input hold (1x clock mode) t/4 a 1 ns (15) notes: (1) see section 4.5.2, ac timing waveforms for waveforms and definitions. (2) see figure 22 for capacitive derating information for output delays and hold times. (3) see figure 23 for capacitive derating information for rise and fall times. (4) where n is the number of n rad ,n rdd ,n wad ,orn wdd wait states that are programmed in the bus controller region table. when there are no wait states in an access, wait never goes active. (5) n e number of wait state inserted with ready . (6) output data and/or dt/r may be driven indefinitely following a cycle if there is no subsequent bus activity. (7) see notes 1, 2 and 3. (8) since asynchronous inputs are synchronized internally by the 80960cf they have no required setup or hold times in order to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1 the setup times shown must be met. asynchronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor. (9) these specifications are guaranteed by the processor. (10) these specifications must be met by the system for proper operation of the processor. (11) this timing is dependent upon the loading of pclk2:1. use the derating curves of figure 22 to adjust the timing for pclk2:1 loading. (12) in the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode. (13) when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than g 0.1% between adjacent cycles. (14) in 2x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the falling edge of the clkin. (see figure 28a.) (15) in 1x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must be deasserted while clkin is high and meet setup and hold times to the rising edge of the clkin. (see figure 28b.) 29
special environment 80960CF-30, -25, -16 4.5.1. ac test conditions cl e 50 pf for all signals 271328 8 figure 9. ac test load the ac specifications in section 4.5 are tested with the 50 pf load shown in figure 9. see figure 16 to see how timings vary with load capacitance. specifications are measured at the 1.5v crossing point, unless otherwise indicated. input waveforms are assumed to have a rise-and-fall time of s 2ns from 0.8v to 2.0v. see section 4.5.2, ac timing waveforms for ac spec definitions, test points and illustrations. 4.5.2. ac timing waveforms 271328 9 figure 10a. input and output clocks waveform 271328 10 figure 10b. clkin waveform 30
special environment 80960CF-30, -25, -16 271328 11 figure 11. output delay and float waveform 271328 12 figure 12a. input setup and hold waveform 271328 13 271328 14 figure 12b. nmi , xint7:0 input setup and hold waveform 31
special environment 80960CF-30, -25, -16 271328 15 figure 13. hold acknowledge timings 271328 16 figure 14. bus back-off (boff ) timings 32
special environment 80960CF-30, -25, -16 271328 17 figure 15. relative timings waveforms 4.5.3 derating curves 271328 18 note: pclk load e 50 pf figure 16. output delay or hold vs load capacitance 33
special environment 80960CF-30, -25, -16 271328 19 (a) all outputs except: lock , dma , sup , holda, breq, (b) lock , dma , sup , holda, breq, dack3:0 , dack3:0 , eop3:0 /tc3:0 , fail eop3:0 /tc3:0 , fail figure 17. rise and fall time derating at highest operating temperature and minimum v cc 271328 20 i cc ei cc under test conditions figure 18. i cc vs frequency and temperature 34
special environment 80960CF-30, -25, -16 5.0 reset, backoff and hold acknowledge the following table lists the condition of each proc- essor output pin while reset is asserted (low). table 10. reset conditions pins state during reset (holda inactive) 1 a31:a2 floating d31:d0 floating be3:0 driven high (inactive) w/r driven low (read) ads driven high (inactive) wait driven high (inactive) blast driven low (active) dt/r driven low (receive) den driven high (inactive) lock driven high (inactive) breq driven low (inactive) d/c floating dma floating sup floating fail driven low (active) dack3 driven high (inactive) dack2 driven high (inactive) dack1 driven high (inactive) dack0 driven high (inactive) eop /tc3 floating (set to input mode) eop /tc2 floating (set to input mode) eop /tc1 floating (set to input mode) eop /tc0 floating (set to input mode) note: (1) with regard to bus output pin state only, the hold ac- knowledge state takes precedence over the reset state. al- though asserting the reset pin will internally reset the processor, the processor's bus output pins will not enter the reset state if it has granted hold acknowledge to a pre- vious hold request (holda is active). furthermore, the processor will grant new hold requests and enter the hold acknowledge state even while in reset. for example, if holda is not active and the processor is in the reset state, then hold is asserted, the processor's bus pins will enter the hold acknowledge state and holda will be granted. the processor will not be able to perform memory accesses until the hold request is re- moved, even if the reset pin is brought high. this opera- tion is provided to simplify boot-up synchronization among multiple processors sharing the same bus. the following table lists the condition of each proc- essor output pin while holda is asserted (low). table 11. hold acknowledge and backoff conditions pins state during holda a31:a2 floating d31:d0 floating be3:0 floating w/r floating ads floating wait floating blast floating dt/r floating den floating lock floating breq driven (high or low) d/c floating dma floating sup floating fail driven high (inactive) dack3 driven high (inactive) dack2 driven high (inactive) dack1 driven high (inactive) dack0 driven high (inactive) eop /tc3 driven if output eop /tc2 driven if output eop /tc1 driven if output eop /tc0 driven if output 35
special environment 80960CF-30, -25, -16 6.0 bus waveforms figure 19. cold reset waveform 271328 21 36
special environment 80960CF-30, -25, -16 figure 20. warm reset waveform 271328 22 37
special environment 80960CF-30, -25, -16 figure 21. entering the once state 271328 23 38
special environment 80960CF-30, -25, -16 271328 24 note: case 1 and case 2 show two possible polarities of pclk2:1. figure 22a. clock synchronization in the 2x clock mode 271328 25 note: in 1x clock mode, the reset pin is actually sampled on the falling edge of 2xclk. 2xclk is an internal signal generat- ed by the pll and is not available on an external pin. therefore, reset is specified relative to the rising edge of clkin. the reset pin is sampled when pclk is high. figure 22b. clock synchronization in the 1x clock mode 39
special environment 80960CF-30, -25, -16 region table entry 271328 26 figure 23. non-burst, non-pipelined requests without wait states 40
special environment 80960CF-30, -25, -16 region table entry 271328 27 figure 24. non-burst, non-pipelined read request with wait states 41
special environment 80960CF-30, -25, -16 region table entry 271328 28 figure 25. non-burst, non-pipelined write request with wait states 42
special environment 80960CF-30, -25, -16 region table entry 271328 29 figure 26. burst, non-pipelined read request without wait states, 32-bit bus 43
special environment 80960CF-30, -25, -16 region table entry 271328 30 figure 27. burst, non-pipelined read request with wait states, 32-bit bus 44
special environment 80960CF-30, -25, -16 region table entry 271328 31 figure 28. burst, non-pipelined write request without wait states, 32-bit bus 45
special environment 80960CF-30, -25, -16 region table entry 271328 32 figure 29. burst, non-pipelined write request with wait states, 32-bit bus 46
special environment 80960CF-30, -25, -16 region table entry 271328 33 figure 30. burst, non-pipelined read request with wait states, 16-bit bus 47
special environment 80960CF-30, -25, -16 region table entry 271328 34 figure 31. burst, non-pipelined read request with wait states, 8-bit bus 48
special environment 80960CF-30, -25, -16 region table entry 271328 35 figure 32. non-burst, pipelined read request without wait states, 32-bit bus 49
special environment 80960CF-30, -25, -16 region table entry 271328 36 figure 33. non-burst, pipelined read request with wait states, 32-bit bus 50
special environment 80960CF-30, -25, -16 region table entry 271328 37 figure 34. burst, pipelined read request without wait states, 32-bit bus 51
special environment 80960CF-30, -25, -16 region table entry 271328 38 figure 35. burst, pipelined read requests with wait states, 32-bit bus 52
special environment 80960CF-30, -25, -16 region table entry 271328 39 figure 36. burst, pipelined read requests with wait states, 16-bit bus 53
special environment 80960CF-30, -25, -16 region table entry 271328 40 figure 37. burst, pipelined read requests with wait states, 8-bit bus 54
special environment 80960CF-30, -25, -16 271328 41 figure 38. using external ready 55
special environment 80960CF-30, -25, -16 271328 42 note: ready adds memory access time to data transfers, whether or not the bus access is a burst access. bterm interrupts a bus access, whether or not the bus access has more data transfers pending. either the ready signal or the bterm signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. figure 39. terminating a burst with bterm 56
special environment 80960CF-30, -25, -16 271328 43 figure 40. boff functional timing 271328 44 figure 41. hold functional timing 57
special environment 80960CF-30, -25, -16 271328 45 notes: 1. case 1: dreq must deassert before dack deasserts. applications are fly-by and some packing and unpacking modes, in which loads are followed by loads, or stores are followed by stores. 2. case 2: dreq must be deasserted by the second clock (rising edge) after dack is driven high. applications are non fly-by transfers and adjacent load-stores or store-loads. 3. dack x is asserted for the duration of a dma bus request. the request may consist of multiple bus accesses (defined by ads and blast . refer to user's manual for ``access'', ``request'' definition. figure 42. dreq and dack functional timing 271328 46 note: eop has the same ac timing requirements as dreq to prevent unwanted dma requests. eop is not edge triggered. eop must be held for a minimum of 2 clock cycles then eop must be deasserted within 15 clock cycles. figure 43. eop functional timing 58
special environment 80960CF-30, -25, -16 271328 47 note: terminal count becomes active during the last bus request of a buffer transfer. if the last load/store bus request is executed as multiple bus accesses, the tc will be active for the entire bus request. refer to the user's manual for further information. figure 44. terminal count functional timing 271328 48 figure 45. fail functional timing 59
special environment 80960CF-30, -25, -16 271328 49 figure 46. a summary of aligned and unaligned transfers for little endian regions 60
special environment 80960CF-30, -25, -16 271328 50 figure 47. a summary of aligned and unaligned transfers for little endian regions (continued) 61
special environment 80960CF-30, -25, -16 figure 48. idle bus operation 271328 51 62

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